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SegLCDLib
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Detailed specifications for each supported LCD controller. For quick selection, see Supported LCDs.
SegTransport.h defines the abstract transport interfaces used by drivers and LCD models.
Arduino transport implementations are declared in SegTransportArduino.h:
Arduino code using these transport classes must include SegTransportArduino.h explicitly.
SEGLCD_DISABLE_ARDUINO_TRANSPORT disables Arduino transport declarations and implementation.
Use it in environments that provide their own SegTransportI2C or SegTransport3Wire implementation and do not have Arduino Wire.h available. Arduino builds should normally leave this undefined.
Driver: SegDriver_PCx85, SegDriver_PCF85134, SegDriver_PCF85176, SegDriver_PCF8576
Note: PCF85134, PCF85176, and PCF8576 share the PCx85 I2C driver model. PCF8576 is an older variant of PCF85176 with identical functionality in this library.
| Property | Value |
|---|---|
| Protocol | I2C (2-wire) |
| I2C Address | 0x38 or 0x39 (SA0 pin) |
| Subaddresses | A0-A2 (protocol subaddress, not I2C) |
| RAM | PCF85134: 60 bytes max address range; PCF85176/PCF8576: 40 bytes (39 usable) |
| Max Segments | Controller/display dependent |
| Power | 3.3V or 5V (controller dependent) |
The I2C address is determined by the SA0 pin only:
A0, A1, A2 are NOT I2C address pins - they are subaddresses used within the communication protocol to select one of 8 devices on the same I2C address.
Finding Address: Use I2C scanner or a PCx85 raw example:
Initialization Sequence:
Command Structure:
Controls how the LCD multiplexer refreshes segments:
| Mode | Duty | Use Case |
|---|---|---|
| Static (1/1) | 100% of segments on at once | Single digit displays (rare) |
| 1/2 Duty | 2 digit rows | Multi-digit displays, simpler |
| 1/3 Duty | 3 digit rows | 6-digit displays (common) |
| 1/4 Duty | 4 digit rows | 4-digit displays |
Higher multiplexing requires more RAM but reduces pin count on LCD module.
Voltage bias between LCD common and segment pins (determines contrast):
| Mode | Voltage Divider | Typical Use |
|---|---|---|
| 1/2 Bias | VDD/2 | Older LCD displays |
| 1/3 Bias | VDD/3 | Modern LCD displays (typical) |
Note: Only affects display when in multiplexed mode (1/2, 1/3, 1/4 duty). Static mode ignores bias.
Each byte controls 8 segments:
Note: I2C pull-ups (4.7kΩ) typically already on LCD module.
Driver: SegDriver_HT1621
| Property | Value |
|---|---|
| Protocol | 3-wire serial (bit-bang GPIO) |
| RAM | 16 bytes |
| Max Segments | 128 (16 × 8) |
| Clock Speed | 32 kHz (typical) |
| Power | 3.3V typical, 5V tolerant |
| Integration | Usually integrated into LCD module (COB) |
Three GPIO pins control communication:
Bit Timing:
Minimum clock period: 100μs (32 kHz max)
Three command types:
Each address holds 8 segments for one digit.
Note: Verify module voltage (3.3V or 5V); most are 3.3V.
Driver: SegDriver_HT1622
| Property | Value |
|---|---|
| Protocol | 3-wire serial (enhanced timing) |
| RAM | 32 bytes |
| Max Segments | 256 (32 × 8) |
| Clock Speed | 32 kHz (typical) |
| Min Pulse Width | 4μs (vs 3.33μs for HT1621) |
| Power | 3.3V typical |
| Integration | Usually integrated into LCD module |
| Feature | HT1621 | HT1622 |
|---|---|---|
| RAM | 16 bytes | 32 bytes |
| Max Digits | 6 (8 segments/digit) | 10-16 (depends on layout) |
| Segment Type | 7-segment | 7 or 16-segment |
| Pulse Width | 3.33μs (typical) | 4μs (minimum) |
HT1622 requires more precise timing:
Bit-banging code must respect 4μs minimum:
Greater RAM supports larger segment displays (16-segment alphanumeric).
Same as HT1621 (3 GPIO pins: CLK, DATA, CS).
Driver: SegDriver_VK0192
| Property | Value |
|---|---|
| Protocol | 3-wire serial, same command/address/data framing family as HT1621/HT1622 |
| RAM | 24 bytes (24 × 8 bit RAM) |
| Max Segments | 192 (24 × 8) |
| Power | 2.4V–5.2V |
| Address Mode | Internal driver uses nibble-style HW write addresses over 24 × 8 bit RAM |
Timing is handled by the shared SegTransport3Wire implementation — the library uses the same clock timing for HT1621, HT1622, and VK0192 (see SegTransportArduino.cpp), so there is no VK0192-specific timing requirement to account for.
The VK0192 controller itself addresses its 24×8 bit RAM sequentially, the same way HT1621/HT1622 do. The reference display module wired up in SegLCD_VK0192_5DigSigBattProgress happens to have its digits spread across non-adjacent RAM addresses, because of how that particular module's SEG/COM pins are wired to the glass:
This is the same kind of module-specific mapping work needed for any segment LCD (HT1621/HT1622 modules can have irregular layouts too) — it is not a property of the VK0192 controller, and other VK0192 modules may map sequentially.
The table above reflects the reference SegLCD_VK0192_5DigSigBattProgress module; other VK0192-based displays may map differently.
Same as HT1621/HT1622 (3 GPIO pins).
Like any segment LCD with a non-trivial physical layout, mapping logical digits/segments to RAM addresses is module-specific work done once per display class:
| Feature | PCF85134 | PCF85176/PCF8576 | HT1621 | HT1622 | VK0192 |
|---|---|---|---|---|---|
| Protocol | I2C | I2C | 3-wire | 3-wire | 3-wire, same framing family as HT1621/HT1622 |
| Pins | 2 (+ power) | 2 (+ power) | 3 | 3 | 3 |
| RAM | 60 bytes max address range | 40 bytes | 16 bytes | 32 bytes | 24 bytes |
| Max Digits | display-dependent | 13 | display-dependent | display-dependent | display-dependent |
| Controller Addressing | Sequential | Sequential | Sequential | Sequential | Sequential |
| Integration | Separate IC | Separate IC | Integrated | Integrated | Integrated |
| Typical Cost | $$$ | $$$ | $$ | $$ | $$ |
Note: whether a specific module's digits/segments land on sequential or scattered RAM addresses depends on how that module's glass is wired to the controller's SEG/COM pins, not on which of these controllers it uses. All three 3-wire controllers use the same clock timing in this library's transport implementation.
Choose PCF85134/PCF85176 if:
Choose HT1621 if:
Choose HT1622 if:
Choose VK0192 if:
Single transaction, all data at once.
Bit-banged protocol, address then data.
Same framing as HT1621, over a 24 × 8 bit RAM. SegLCDLib uses internal HW write addresses that advance in half-byte steps for compatibility with the existing driver model.